Semiconductor device

ABSTRACT

A semiconductor device of an embodiment includes an n-type SiC region, a metal layer, and a conductive layer provided between the n-type SiC region and the metal layer, the conductive layer including titanium (Ti), oxygen (O), at least one first element from zirconium (Zr) and hafnium (Hf), and at least one second element from vanadium (V), niobium (Nb), and tantalum (Ta).

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority fromJapanese Patent Application No. 2015-179034, filed on Sep. 11, 2015, theentire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor device.

BACKGROUND

SiC (silicon carbide) is expected as a material for a next generationsemiconductor device. SiC, compared with Si (silicon), has excellentphysical properties of three times band gap, about ten times breakdownfield strength, about three times thermal conductivity. By utilizingthis property, it is possible to achieve a semiconductor device with alow loss and capable of high temperature operation.

However, in a semiconductor device using SiC, compared with asemiconductor device using Si, there is a problem that contactresistance increases between a semiconductor region and a metalelectrode.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic cross-sectional diagram illustrating asemiconductor device in a first embodiment;

FIG. 2 is an explanatory diagram of a function and effect of thesemiconductor device in the first embodiment;

FIG. 3 is an explanatory diagram of the function and effect of thesemiconductor device in the first embodiment;

FIG. 4 is an explanatory diagram of a function and effect of asemiconductor device in a second embodiment;

FIG. 5 is a schematic cross-sectional diagram illustrating asemiconductor device in a third embodiment;

FIG. 6 is a schematic cross-sectional diagram illustrating asemiconductor device in a fifth embodiment;

FIG. 7 is a schematic cross-sectional diagram illustrating asemiconductor device in a seventh embodiment;

FIG. 8 is a schematic cross-sectional diagram illustrating asemiconductor device in a ninth embodiment; and

FIG. 9 is a schematic cross-sectional diagram illustrating asemiconductor device in an eleventh embodiment.

DETAILED DESCRIPTION

A semiconductor device of an embodiment includes an n-type SiC region, ametal layer; and a conductive layer provided between the n-type SiCregion and the metal layer, the conductive layer including titanium(Ti), oxygen (O), at least one first element from zirconium (Zr) andhafnium (Hf), and at least one second element from vanadium (V), niobium(Nb), and tantalum (Ta).

Hereinafter, embodiments of the present disclosure are described withreference to the drawings. Incidentally, in description below, the sameor similar members are referenced by the same reference numerals, andthe description of the members once described is appropriately omitted.

In addition, in the description below, notations of n⁺, n, n⁻, and p⁺,p, p⁻ represent relative elevations of impurity concentrations inrespective conductivity types. That is, it represents that n⁺ isrelatively higher than n in an n-type impurity concentration, and n⁻ isrelatively lower than n in the n-type impurity concentration. Inaddition, it represents that p⁺ is relatively higher than p in a p-typeimpurity concentration, and p⁻ is relatively lower than p in the p-typeimpurity concentration. Incidentally, n⁺-type, n⁻-type may simply bereferred to as n-type, and p⁺-type, p⁻-type may simply be referred to asp-type.

First Embodiment

A semiconductor device of the present embodiment includes an n-type SiCregion, a metal layer, and a conductive layer provided between then-type SiC region and the metal layer. The conductive layer includestitanium (Ti), oxygen (O), at least one first element from zirconium(Zr) and hafnium (Hf), and at least one second element from vanadium(V), niobium (Nb), and tantalum (Ta).

FIG. 1 is a schematic cross-sectional diagram illustrating aconfiguration of a PIN diode being a semiconductor device of the presentembodiment.

A PIN diode 100 includes an SiC layer 10, an anode electrode 12, acathode electrode (metal layer) 14, and a conductive layer 16. The SiClayer 10 includes a cathode region (n-type SiC region) 18, a driftregion 20, and an anode region 22.

The SiC layer 10 is of SiC whose crystal structure is 4H-SiC. The 4H-SiCis a hexagonal crystal system.

The SiC layer 10 has a first plane and a second plane. In FIG. 1, thefirst plane is an upper plane of the figure, and the second plane is alower plane of the figure. The first plane is referred to as a frontplane, and the second plane is referred to as a back plane.

An example is described of a case in which the first plane is a planeinclined to a (0001) face by equal to or greater than 0 degrees andequal to or less than 8 degrees, and the second plane is a planeinclined to (000-1) face by equal to or greater than 0 degrees and equalto or less than 8 degrees. The (0001) face is referred to as a siliconface. The (000-1) face is referred to as a carbon face.

The cathode region (n-type SiC region) 18 is of n-type SiC. The cathoderegion 18 contains, for example, nitrogen (N) as an n-type impurity. Aconcentration of the n-type impurity of the cathode region 18 is equalto or greater than 1×10¹⁸ cm⁻³ and equal to or less than 1×10²¹ cm⁻³.

From a viewpoint of reducing contact resistance between the cathodeelectrode (metal layer) 14 and the cathode region 18, a concentration ofthe n-type impurity in the second plane of the cathode region 18 isdesirably equal to or greater than 1×10¹⁹ cm⁻³, and is more desirablyequal to or greater than 1×10²⁰ cm⁻³.

The drift region 20 is provided on the cathode region 18. The driftregion 20 is of, for example, n⁻-type SiC formed by epitaxial growth onthe cathode region 18. Thickness of the drift region 20 is, for example,equal to or greater than 5 μm and equal to or less than 150 μm.

The drift region 20 contains, for example, nitrogen (N) as an n-typeimpurity. A concentration of the n-type impurity of the drift region 20is, for example, equal to or greater than 5×10¹⁵ cm⁻³ and equal to orless than 2×10¹⁶ cm⁻³.

The anode region 22 is provided on the drift region 20. The anode region22 is of, for example, p-type SiC formed by epitaxial growth on thedrift region 20. Thickness of the anode region 22 is, for example, equalto or greater than 0.2 μm and equal to or less than 0.6 μm.

The anode region 22 contains, for example, aluminum (Al) as a p-typeimpurity. An impurity concentration of the anode region 22 is, forexample, equal to or greater than 1×10¹⁸ cm⁻³ and equal to or less than1×10²¹ cm⁻³.

From a viewpoint of reducing contact resistance between the anodeelectrode 12 and the anode region 22, the concentration of the n-typeimpurity in the second plane of the cathode region 18 is desirably equalto or greater than 1×10¹⁹ cm⁻³, and is more desirably equal to orgreater than 1×10²⁰ cm⁻³.

The anode electrode 12 is provided on the front plane of the SiC layer10. The anode electrode 12 is provided on the anode region 22. The anodeelectrode 12 is electrically connected with the anode region 22.

The anode electrode 12 is of metal. The metal forming the anodeelectrode 12 is of, for example, a laminated structure of titanium (Ti)and aluminum (Al). The metal forming the anode electrode 12 may reactwith the SiC layer 10 to form metal silicide or metal carbide.

The cathode electrode (metal layer) 14 is provided on the back plane ofthe SiC layer 10. The cathode electrode 14 is electrically connectedwith the cathode region 18.

The cathode electrode 14 is of metal. The metal forming the cathodeelectrode 14 is of, for example, titanium nitride (TiN).

The conductive layer 16 is provided between the cathode region (n-typeSiC region) 18 and the cathode electrode (metal layer) 14. Theconductive layer 16 is in contact with the cathode region 18. Theconductive layer 16 is in contact with the cathode electrode 14.

The conductive layer 16 contains titanium (Ti) and oxygen (O). Inaddition, the conductive layer 16 contains zirconium (Zr) or hafnium(Hf). In addition, the conductive layer 16 contains at least one elementselected from the group consisting of vanadium (V), niobium (Nb), andtantalum (Ta).

The conductive layer 16 is of metal oxide. The conductive layer 16 isof, for example, titanium oxide. The conductive layer 16 is of, forexample, (Ti,Zr,Hf)O₃. The conductive layer 16 is of polycrystal oramorphous.

Thickness of the conductive layer 16 is, for example, equal to orgreater than 10 nm and equal to or less than 100 nm.

An atomic ratio of titanium to titanium, zirconium, and hafnium in theconductive layer 16 (Ti/(Ti+Zr+Hf)) is desirably equal to or greaterthan 0.5 and equal to or less than 0.8, and is more desirably equal toor greater than 0.6 and equal to or less than 0.7.

Due to the fact that an element is added to metal oxide, the metal oxideincludes conductivity. For example, due to the fact that vanadium (V),niobium (Nb), or tantalum (Ta), which becomes an n-type impurity bysubstituting titanium (Ti), zirconium (Zr), or hafnium (Hf), is added tometal oxide, the metal oxide includes n-type conductivity in which anelectron is a carrier.

A concentration of the element in the conductive layer 16 is, forexample, equal to or greater than 1×10¹⁸ cm⁻³ and equal to or less than1×10²¹ cm⁻³. The concentration of the element in the conductive layer16, from a viewpoint of reducing electric resistance of the conductivelayer 16, is desirably equal to or greater than 1×10¹⁹ cm⁻³, and is moredesirably equal to or greater than 1×10²⁰ cm⁻³.

It is possible to identify a type of the element, amount of the element,atomic ratio of the element contained in the conductive layer 16, bySecondary Ion Mass Spectrometry (SIMS).

The conductive layer 16 can be formed, for example, by a sputteringmethod at equal to or less than 400° C. In this state, the conductivelayer 16 is of amorphous. After that, crystallization annealing (600° C.to 800° C.) can be performed. In addition, a polycrystalline film can beformed by growing the film to have good coverage, with a CVD method, andperforming crystallization annealing. At that time, although thepolycrystalline film can be columnar in the film thickness direction, ifthe polycrystalline film is made to be a laminated structure of two ormore layers in which sizes of columns are varied, uniformity in a filmplane of electrical properties of the film is increased. The laminatedstructure in which the sizes of the columns are varied can be formed byperforming a plurality of times of deposition, as deposition,crystallization, deposition (condition of different temperature),crystallization. This is the same in the following embodiments.

Hereinafter, the function and effect are described of the semiconductordevice of the present embodiment.

To increase ON-state current of the PIN diode 100, it is desirable toreduce the contact resistance between the anode electrode 12 and theanode region 22, or the cathode electrode 14 and the cathode region 18.To reduce the contact resistance, it is desirable to achieve ohmiccontact.

The cathode region 18 is of n-type SiC. To achieve the ohmic contactbetween the cathode electrode 14 and the cathode region 18, it isdesirable that a work function of the metal forming the cathodeelectrode 14 coincides with electron affinity of SiC. In this case, anenergy barrier disappears between the cathode electrode 14 and thecathode region 18, so that the ohmic contact can be achieved.

Incidentally, the work function is an energy difference between a vacuumlevel (the energy level of the vacuum) and a Fermi level of a targetedsubstance. In addition, the electron affinity is a difference betweenthe vacuum level (the energy level of the vacuum) and an energy level ofthe lower end of the conduction band of the targeted substance.

In a case of 4H-SiC, the electron affinity is 3.60 eV. Therefore, theohmic contact can be achieved by applying a metal whose work function isapproximately 3.60 eV for the metal forming the cathode electrode 14.

However, in the metal whose work function is approximately 3.60 eV, froma viewpoint of resistance to oxidation, resistance to moisture, and thelike, there is no suitable metal as an electrode for contact. Inaddition, the cathode electrode 14, after forming the anode electrode 12on the front plane of the SiC layer 10, is formed on the back plane ofSiC layer 10. Because of this, it is desirable that the ohmic contactbetween the cathode electrode 14 and the cathode region 18 can be formedby a low temperature process.

FIG. 2, FIG. 3 are explanatory diagrams of the function and effect ofthe semiconductor device of the present embodiment.

FIG. 2 is a diagram illustrating a change of electron affinity oftitanium oxide when zirconium (Zr) or hafnium (Hf) is added to thetitanium oxide. The electron affinity is calculated by using firstprinciples calculation.

Incidentally, when metal oxide such as titanium oxide is metalized byintroducing an n-type impurity, it can be regarded that the Fermi levelof the titanium oxide coincides with the energy level of the lower endof the conduction band. Because of this, it is possible to regard thatthe work function of the metal oxide coincides with the electronaffinity.

FIG. 3 is a diagram illustrating energy band structure of silicon (Si),4H-SiC, zirconium oxide (ZrO₃), hafnium oxide (HfO₃), titanium oxide(TiO₃). FIG. 3 illustrates the energy difference (electron affinity)between the vacuum level and the lower end of the conduction band, theenergy difference between the vacuum level and the upper end of thevalence band, band gap energy of each material. In the figure, thenumeric value in parentheses represents the band gap energy.

As illustrated in FIG. 2, as a result of the first principlescalculation by the inventors, it has been revealed that the electronaffinity is changed in a direction to be reduced by adding zirconium(Zr) or hafnium (Hf) to titanium oxide. When zirconium (Zr) or hafnium(Hf) is not added, that is, when it is titanium oxide, the electronaffinity is 4.15 eV. On the other hand, when titanium (Ti) of titaniumoxide is entirely substituted by zirconium (Zr) or hafnium (Hf), thatis, when it is zirconium oxide or hafnium oxide, the electron affinityis lowered to 2.55 V.

As illustrated in FIG. 3, by adding zirconium (Zr) or hafnium (Hf) totitanium oxide, it is possible to set the electron affinity to any valuebetween 2.55 eV and 4.15 eV, which is indicated by a white arrow. Inother words, by changing the atomic ratio of titanium to titanium,zirconium, and hafnium (Ti/(Ti+Zr+Hf)) of (Ti,Zr,Hf)O₃, it is possibleto set the electron affinity to any value between 2.55 eV and 4.15 eV,which is indicated by the white arrow. In particular, by makingTi/(Ti+Zr+Hf)=0.64, it is possible to allow the electron affinity tocoincide with electron affinity of 4H-SiC, 3.60 eV.

In the present embodiment, the conductive layer 16 is provided betweenthe cathode electrode 14 and the cathode region 18. In the conductivelayer 16, zirconium (Zr) or hafnium (Hf) is added to a metal oxidecontaining titanium. Thus, the work function is reduced in comparisonwith a case in which metal oxide does not contain zirconium (Zr) orhafnium (Hf). Therefore, the work function of the conductive layer 16can be made closer to the electron affinity of 4H-SiC, 3.60 eV.Therefore, a barrier is lowered between the cathode region 18 and theconductive layer 16, and contact resistance is reduced between thecathode region 18 and the conductive layer 16.

Since contact between the conductive layer 16 and the cathode electrode14 becomes contact between metal and metal, a low contact resistance isachieved. The contact between the conductive layer 16 and the cathodeelectrode 14 becomes the ohmic contact. Since the contact between theconductive layer 16 and the cathode electrode 14 becomes the contactbetween metal and metal, it is possible to select a metal materialforming the cathode electrode 14 without considering the contactresistance to the cathode region 18.

From a viewpoint of reducing contact resistance between the cathoderegion 18 and the conductive layer 16 to achieve the ohmic contact, theatomic ratio of titanium to titanium, zirconium, and hafnium in theconductive layer 16 (Ti/(Ti+Zr+Hf)) is desirably equal to or greaterthan 0.5 and equal to or less than 0.8, and is more desirably equal toor greater than 0.6 and equal to or less than 0.7. If the atomic ratio(Ti/(Ti+Zr+Hf)) is equal to or greater than 0.5 and equal to or lessthan 0.8, it is possible to regulate the work function of the conductivelayer 16 in a range of 3.60 eV ±10%.

In addition, from the viewpoint of reducing the contact resistancebetween the cathode region 18 and conductive layer 16 to achieve theohmic contact, the concentration of the n-type impurity in the secondplane of the cathode region 18 is desirably equal to or greater than1×10¹⁹ cm⁻³, and is more desirably equal to or greater than 1×10¹⁰ cm⁻³.

As described above, according to the present embodiment, the PIN diode100 is achieved of a low contact resistance between the cathodeelectrode 14 and the cathode region 18.

In addition, the conductive layer 16 of the present embodiment can bedeposited by, for example, the sputtering method at equal to or lessthan 400° C. In this state, the conductive layer 16 is of amorphous.After that, crystallization annealing (600° C. to 800° C.) can beperformed. In addition, a polycrystalline film can be formed by growingthe film to have good coverage, with a CVD method, and performingcrystallization annealing. At that time, although the polycrystallinefilm can be columnar in the film thickness direction, if thepolycrystalline film is made to be the laminated structure of two ormore layers in which the sizes of the columns are varied, the uniformityin the film plane of the electrical properties of the film is increased.In particular, for the PTCR effect, it is important that apolycrystalline interface uniformly exists, and it is effective to makethe laminated structure of the polycrystalline film of two or morelayers in which the sizes of columns are varied. This is the same in thefollowing embodiments. Therefore, the PIN diode 100 is achieved of thelow contact resistance with a relatively low temperature process.

Second Embodiment

A semiconductor device of the present embodiment includes an n-type SiCregion, a metal layer, and a conductive layer provided between then-type SiC region and the metal layer. The conductive layer includestitanium (Ti), oxygen (O), at least one first element from zirconium(Zr) and hafnium (Hf), at least one metal element from calcium (Ca),strontium (Sr), and barium (Ba), and at least one second element fromvanadium (V), niobium (Nb), tantalum (Ta), scandium (Sc), yttrium (Y),and lanthanoid.

The semiconductor device of the present embodiment is the same as thesemiconductor device of the first embodiment, except that the conductivelayer contains at least one metal element selected from the groupconsisting of calcium (Ca), strontium (Sr), and barium (Ba), and thatelements are different from those that can be contained in theconductive layer. Therefore, description is omitted of contentsoverlapping with those of the first embodiment.

The semiconductor device of the present embodiment is a PIN diode. ThePIN diode of the present embodiment is described with reference to FIG.1.

A conductive layer 16 is provided between a cathode region (n-type SiCregion) 18 and a cathode electrode (metal layer) 14. The conductivelayer 16 is in contact with the cathode region 18. The conductive layer16 is in contact with the cathode electrode 14.

The conductive layer 16 contains at least one metal element selectedfrom the group consisting of calcium (Ca), strontium (Sr), and barium(Ba). In addition, the conductive layer 16 contains titanium (Ti) andoxygen (O). In addition, the conductive layer 16 contains zirconium (Zr)or hafnium (Hf). In addition, the conductive layer 16 contains at leastone element selected from the group consisting of vanadium (V), niobium(Nb), tantalum (Ta), scandium (Sc), yttrium (Y), and lanthanoid.

The conductive layer 16 is of metal oxide. The conductive layer 16 isof, for example, calcium titanate, strontium titanate, barium titanate,or a composite thereof. The conductive layer 16 is of, for example,(Ca,Sr,Ba)(Ti,Zr,Hf)O₃ including perovskite structure. The conductivelayer 16 is of polycrystal or amorphous.

Thickness of the conductive layer 16 is, for example, equal to orgreater than 10 nm and equal to or less than 100 nm.

An atomic ratio of titanium to titanium, zirconium, and hafnium in theconductive layer 16 (Ti/(Ti+Zr+Hf)) is desirably equal to or greaterthan 0.5 and equal to or less than 0.8, and is more desirably equal toor greater than 0.6 and equal to or less than 0.7.

Due to the fact that an element is added to metal oxide, the metal oxideincludes conductivity. For example, due to the fact that vanadium (V),niobium (Nb), or tantalum (Ta), which becomes an n-type impurity bysubstituting titanium (Ti), zirconium (Zr), or hafnium (Hf), is added tometal oxide, the metal oxide includes n-type conductivity in which anelectron is a carrier. In addition, for example, due to the fact thatscandium (Sc), yttrium (Y), or lanthanoid, which become the n-typeimpurity by substituting calcium (Ca), strontium (Sr), or barium (Ba),is added to metal oxide, the metal oxide includes the n-typeconductivity in which the electron is the carrier. Incidentally,lanthanoid includes lanthanum (La), cerium (Ce), praseodymium (Pr),neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu),gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium(Er), thulium (Tm), ytterbium (Yb), lutetium (Lu).

A concentration of the element in the conductive layer 16 is, forexample, equal to or greater than 1×10¹⁸ cm⁻³ and equal to or less than1×10²¹ cm⁻³. The concentration of the element in the conductive layer16, from a viewpoint of reducing electric resistance of the conductivelayer 16, is desirably equal to or greater than 1×10¹⁹ cm⁻³, and is moredesirably equal to or greater than 1×10²⁰ cm⁻³.

It is possible to identify a type of the element, amount of the element,atomic ratio of the element contained in the conductive layer 16, by theSIMS.

The conductive layer 16 can be formed, for example, by a sputteringmethod at equal to or less than 400° C. In this state, the conductivelayer 16 is of amorphous. After that, crystallization annealing (600° C.to 800° C.) can be performed. In addition, a polycrystalline film can beformed by growing the film to have good coverage, with a CVD method, andperforming crystallization annealing. At that time, although thepolycrystalline film can be columnar in the film thickness direction, ifthe polycrystalline film is made to be a laminated structure of two ormore layers in which sizes of columns are varied, uniformity in a filmplane of electrical properties of the film is increased. In particular,for the PTCR effect, it is important that a polycrystalline interfaceuniformly exists, and it is effective to make the laminated structure ofthe polycrystalline film of two or more layers in which the sizes ofcolumns are varied. It is the same in the following embodiments.

Hereinafter, the function and effect are described of the semiconductordevice of the present embodiment.

In the PIN diode of the present embodiment, same as the firstembodiment, in the conductive layer 16, zirconium (Zr) or hafnium (Hf)is added to a metal oxide containing titanium. Thus, the work functionof the metal oxide is reduced in comparison with a case in which themetal oxide does not contain zirconium (Zr) or hafnium (Hf). The effectof reducing the work function is achieved similarly even in a case inwhich calcium (Ca), strontium (Sr), or barium (Ba) is contained in themetal oxide. Therefore, the PIN diode is achieved of a low contactresistance between the cathode electrode 14 and the cathode region 18.

FIG. 4 is a diagram for describing the function and effect of thesemiconductor device of the present embodiment. FIG. 4 is a diagramillustrating temperature dependency of the electric resistance of theconductive layer 16 of the present embodiment.

The conductive layer 16 of the present embodiment is of, for example,calcium titanate, strontium titanate, or barium titanate. Calciumtitanate, strontium titanate, barium titanate, and a composite thereof,as illustrated in FIG. 4, include a property in which the temperaturedependency of the electric resistance turns from negative dependency topositive dependency. In other words, the conductive layer 16 of thepresent embodiment is of a resistor including a positive temperaturecoefficient (Positive Temperature Coefficient Resistor: PTCR) in a hightemperature region.

For example, when excess current flows through the PIN diode, the PINdiode may be broken down by generation of heat due to the excesscurrent. In the PIN diode of the present embodiment, the conductivelayer 16 is of the PTCR. Therefore, if heat is generated when the excesscurrent flows, the electric resistance of the conductive layer 16 isincreased. Therefore, current flowing through the PIN diode issuppressed, and breakdown due to the excess current of the PIN diode issuppressed.

In an operation temperature region of the PIN diode, it is desirablethat the electric resistance of the conductive layer 16 includes notemperature dependency or negative temperature dependency so thatON-state current of the PIN diode is not decreased. In addition, it isdesirable that the temperature dependency of the electric resistance ofthe conductive layer 16 turns to the positive dependency before the PINdiode is broken down by temperature increase. From the viewpoints above,it is desirable that the temperature dependency of the electricresistance of the conductive layer 16 turns from the negative dependencyto the positive dependency at a temperature equal to or greater than150° C. and equal to or less than 200° C.

It is desirable that the conductive layer 16 contains lead (Pb). Incalcium titanate, strontium titanate, barium titanate, and the compositethereof, by containing lead (Pb), it becomes possible to shift a regionincluding the positive temperature coefficient to the high temperatureside.

As described above, according to the present embodiment, the PIN diodeis achieved of the low contact resistance between the cathode electrode14 and the cathode region 18. In addition, the PIN diode is achieved ofthe low contact resistance with a relatively low temperature process.Further, due to the fact that the conductive layer 16 is of the PTCR,the breakdown due to the excess current of the PIN diode is suppressed.

Third Embodiment

A semiconductor device of the present embodiment is different from thesemiconductor device of the first embodiment, in that the device is aMOSFET. Description is omitted of contents overlapping with those of thefirst embodiment, such as the configuration, function of the conductivelayer.

FIG. 5 is a schematic cross-sectional diagram illustrating aconfiguration of the MOSFET being the semiconductor device of thepresent embodiment. A MOSFET (Metal Oxide Semiconductor Field EffectTransistor) 200 is, for example, a Double Implantation MOSFET(DIMOSFET), in which a well region and a source region are formed by ionimplantation.

A MOSFET 200 includes an SiC layer 10, a source electrode (second metallayer) 32, a drain electrode (first metal layer) 34, a gate insulatingfilm 36, a gate electrode 38, an interlayer insulating film 40, a firstconductive layer 42, a second conductive layer 44. The SiC layer 10includes a drain region (n-type first SiC region) 46, a drift region 48,a well region 50, a source region (n-type second SiC region) 52, a wellcontact region (p-type SiC region) 54.

The SiC layer 10 is of SiC whose crystal structure is 4H-SiC. The 4H-SiCis a hexagonal crystal system.

The SiC layer 10 has a first plane and a second plane. In FIG. 5, thefirst plane is an upper plane of the figure, and the second plane is alower plane of the figure. Hereinafter, the first plane is referred toas a front plane, and the second plane is referred to as a back plane.

An example is described of a case in which the first plane is a planeinclined to a (0001) face by equal to or greater than 0 degrees andequal to or less than 8 degrees, and the second plane is a planeinclined to (000-1) face by equal to or greater than 0 degrees and equalto or less than 8 degrees. The (0001) face is referred to as a siliconface. The (000-1) face is referred to as a carbon face.

The drain region (n-type SiC region) 46 is of n-type SiC. The drainregion 46 contains, for example, nitrogen (N) as an n-type impurity. Aconcentration of the n-type impurity of the drain region 46 is, forexample, equal to or greater than 1×10¹⁸ cm⁻³ and equal to or less than1×10²¹ cm⁻³.

From a viewpoint of reducing contact resistance between the drainelectrode 34 and the drain region 46, a concentration of the n-typeimpurity in the second plane of the drain region 46 is desirably equalto or greater than 1×10¹⁹ cm⁻³, and is more desirably equal to orgreater than 1×10²⁰ cm⁻³.

The drift region 48 is provided on the drain region 46. The drift region48 is of, for example, n⁻-type SiC formed by epitaxial growth on thedrain region 46. Thickness of the drift region 48 is, for example, equalto or greater than 5 μm and equal to or less than 150 μm.

The drift region 48 contains, for example, nitrogen (N) as an n-typeimpurity. A concentration of the n-type impurity of the drift region 48is, for example, equal to or greater than 5×10¹⁵ cm⁻³ and equal to orless than 2×10¹⁶ cm⁻³.

The well region 50 is provided on the drift region 48. The well region50 is of p-type SiC. The well region 50 functions as a channel region ofthe MOSFET 200.

The well region 50 contains, for example, aluminum (Al) as a p-typeimpurity. A concentration of the p-type impurity of the well region 50is equal to or greater than 5×10¹⁵ cm⁻³ and equal to or less than 1×10¹⁷cm⁻³. Depth of the well region 50 is, for example, equal to or greaterthan 0.4 μm and equal to or less than 0.8 μm.

The source region 52 is provided in the well region 50. The sourceregion 52 is of n⁺-type SiC. The source region 52 contains, for example,nitrogen (N) as an n-type impurity. A concentration of the n-typeimpurity of the source region 52 is, for example, equal to or greaterthan 1×10¹⁸ cm⁻³ and equal to or less than 1×10²¹ cm⁻³.

From a viewpoint of reducing contact resistance between the sourceelectrode 32 and the source region 52, a concentration of the n-typeimpurity in the first plane of the source region 52 is desirably equalto or greater than 1×10¹⁹ cm⁻³, and is more desirably equal to orgreater than 1×10²⁰ cm⁻³.

Depth of the source region 52 is shallower than depth of the well region50, and is, for example, equal to or greater than 0.2 μm and equal to orless than 0.4 m.

The well contact region 54 is provided in the well region 50. The wellcontact region 54 is provided laterally to the source region 52.

The well contact region 54 is of p⁺-type SiC. The well contact region 54contains, for example, aluminum (Al) as a p-type impurity. Aconcentration of the p-type impurity of the well contact region 54 is,for example, equal to or greater than 1×10¹⁸ cm⁻³ and equal to or lessthan 1×10²¹ cm⁻³.

Depth of the well contact region 54 is shallower than depth of the wellregion 50, and is, for example, equal to or greater than 0.2 μm andequal to or less than 0.4 μm.

The gate insulating film 36 is formed on the front planes of the driftregion 48 and the well region 50. For the gate insulating film 36, forexample, a silicon oxide film and a high-k insulating film can beapplied.

The gate electrode 38 is provided on the gate insulating film 36. Forthe gate electrode 38, for example, polycrystalline silicon doped withan impurity can be applied.

The interlayer insulating film 40 is provided on the gate electrode 38.The interlayer insulating film 40 is of, for example, a silicon oxidefilm.

The well region 50 sandwiched between the source region 52 and the driftregion 48 below the gate electrode 38, functions as the channel regionof the MOSFET 200.

The source electrode 32 is provided on the front plane of the SiC layer10. The source electrode 32 is electrically connected with the sourceregion 52 and the well contact region 54. The source electrode 32 is incontact with the well contact region 54 and the second conductive layer44. The source electrode 32 also includes a function of applyingelectrical potential to the well region 50.

The source electrode 32 is of metal. The metal forming the sourceelectrode 32 is of, for example, a laminated structure of titanium (Ti)and aluminum (Al). The metal forming the source electrode 32 may reactwith the SiC layer 10 to form metal silicide or metal carbide.

The drain electrode 34 is provided on the back plane of the SiC layer10. The drain electrode 34 is electrically connected with the drainregion 46.

The drain electrode 34 is of metal. The metal forming the drainelectrode 34 is, for example, titanium nitride (TiN).

The first conductive layer 42 is provided between the drain region(n-type first SiC region) 46 and the drain electrode (first metal layer)34. The first conductive layer 42 is in contact with the drain region46. The first conductive layer 42 is in contact with the drain electrode34.

The second conductive layer 44 is provided between the source region(n-type second SiC region) 52 and the source electrode (second metallayer) 32. The second conductive layer 44 is in contact with the sourceregion 52. The second conductive layer 44 is in contact with the sourceelectrode 32.

The first conductive layer 42 and the second conductive layer 44 containtitanium (Ti), oxygen (O), zirconium (Zr) or hafnium (Hf), and at leastone element selected from the group consisting of vanadium (V), niobium(Nb), and tantalum (Ta).

As described above, according to the present embodiment, the MOSFET 200is achieved of a low contact resistance between the drain electrode 34and the drain region 46. In addition, the MOSFET 200 is achieved of alow contact resistance between the source electrode 32 and the sourceregion 52. In addition, the MOSFET 200 is achieved of the low contactresistance with a relatively low temperature process.

Further, to the n⁺-type source region 52 and the p⁺-type well contactregion 54, contact can be achieved of a low contact resistance by thesource electrode 32 simultaneously. Since contact between the secondconductive layer 44 and the source electrode 32 becomes contact betweenmetal and metal, it is possible to select a metal material forming thesource electrode 32 without considering the contact resistance.Therefore, as the metal material of the source electrode 32, a metalmaterial can be selected of reducing the contact resistance to the wellcontact region 54.

Fourth Embodiment

A semiconductor device of the present embodiment is the same as thesemiconductor device of the third embodiment, except that first andsecond conductive layers contain at least one metal element selectedfrom the group consisting of calcium (Ca), strontium (Sr), and barium(Ba), and that elements are different from those that can be containedin the first and second conductive layers. Therefore, description isomitted of contents overlapping with those of the third embodiment. Inaddition, for the configuration, function, and the like of theconductive layer, description is omitted of contents overlapping withthose of the first or second embodiment.

The semiconductor device of the present embodiment is a MOSFET. TheMOSFET of the present embodiment is described with reference to FIG. 5.

A first conductive layer 42 and a second conductive layer 44 contain atleast one metal element selected from the group consisting of calcium(Ca), strontium (Sr), and barium (Ba). In addition, the first conductivelayer 42 and the second conductive layer 44 contain titanium (Ti) andoxygen (O). In addition, the first conductive layer 42 and secondconductive layer 44 contain zirconium (Zr) or hafnium (Hf). In addition,the first conductive layer 42 and the second conductive layer 44 containat least one element selected from the group consisting of vanadium (V),niobium (Nb), tantalum (Ta), scandium (Sc), yttrium (Y), and lanthanoid.

The first conductive layer 42 and the second conductive layer 44 are ofmetal oxide. The first conductive layer 42 and the second conductivelayer 44 are of, for example, calcium titanate, strontium titanate,barium titanate, or a composite thereof. The first conductive layer 42and the second conductive layer 44 are of, for example,(Ca,Sr,Ba)(Ti,Zr,Hf)O₃ including perovskite structure. The firstconductive layer 42 and the second conductive layer 44 are ofpolycrystal or amorphous.

The first conductive layer 42 and the second conductive layer 44 are ofthe PTCR.

As described above, according to the present embodiment, the MOSFET isachieved of a low contact resistance between a drain electrode 34 and adrain region 46. In addition, the MOSFET is achieved of a low contactresistance between a source electrode 32 and a source region 52. Inaddition, the MOSFET is achieved of the low contact resistance with arelatively low temperature process.

Further, to the n⁺-type source region 52 and a p⁺-type well contactregion 54, contact can be achieved of a low contact resistance by thesource electrode 32 simultaneously. Further, due to the fact that thefirst conductive layer 42 and the second conductive layer 44 are of thePTCR, breakdown due to excess current of the MOSFET is suppressed.

Fifth Embodiment

A semiconductor device of the present embodiment is different from thesemiconductor device of the third embodiment, in that the device is aMOSFET of a trench gate structure. Description is omitted of contentsoverlapping with those of the third embodiment.

FIG. 6 is a schematic cross-sectional diagram illustrating aconfiguration of the MOSFET being the semiconductor device of thepresent embodiment. A MOSFET 300 is the MOSFET of the trench gatestructure in which a gate electrode is provided in the trench.

The MOSFET 300 includes an SiC layer 10, a source electrode (secondmetal layer) 32, a drain electrode (first metal layer) 34, a gateinsulating film 36, a gate electrode 38, an interlayer insulating film40, a first conductive layer 42, a second conductive layer 44. The SiClayer 10 includes a drain region (n-type first SiC region) 46, a driftregion 48, a well region 50, a source region (n-type second SiC region)52, a well contact region (p-type SiC region) 54.

The gate insulating film 36 and the gate electrode 38 are formed in atrench 60 provided in the SiC layer 10.

The first conductive layer 42 and the second conductive layer 44 containtitanium (Ti), oxygen (O), zirconium (Zr) or hafnium (Hf), and at leastone element selected from the group consisting of vanadium (V), niobium(Nb), and tantalum (Ta).

According to the present embodiment, same as the third embodiment, theMOSFET 300 is achieved of a low contact resistance between the drainelectrode 34 and the drain region 46. In addition, same as the thirdembodiment, the MOSFET 300 is achieved of a low contact resistancebetween the source electrode 32 and the source region 52. In addition,same as the third embodiment, the MOSFET 300 is achieved of the lowcontact resistance with a relatively low temperature process.

Further, same as the third embodiment, to the n⁺-type source region 52and the p⁺-type well contact region 54, contact can be achieved of a lowcontact resistance by the source electrode 32 simultaneously.

Further, by the trench gate structure, the MOSFET 300 is achieved of alarge ON-state current.

Sixth Embodiment

A semiconductor device of the present embodiment is the same as thesemiconductor of the fifth embodiment, except that first and secondconductive layers contain at least one metal element selected from thegroup consisting of calcium (Ca), strontium (Sr), and barium (Ba), andthat elements are different from those that can be contained in thefirst and second conductive layers. Therefore, description is omitted ofcontents overlapping with those of the fifth embodiment. In addition,for the configuration, function, and the like of the conductive layer,description is omitted of contents overlapping with those of the firstor second embodiment.

The semiconductor device of the present embodiment is a MOSFET. TheMOSFET of the present embodiment is described with reference to FIG. 6.

A first conductive layer 42 and a second conductive layer 44 contain atleast one metal element selected from the group consisting of calcium(Ca), strontium (Sr), and barium (Ba). In addition, the first conductivelayer 42 and the second conductive layer 44 contain titanium (Ti) andoxygen (O). In addition, the first conductive layer 42 and secondconductive layer 44 contain zirconium (Zr) or hafnium (Hf). In addition,the first conductive layer 42 and the second conductive layer 44 containat least one element selected from the group consisting of vanadium (V),niobium (Nb), tantalum (Ta), scandium (Sc), yttrium (Y), and lanthanoid.

The first conductive layer 42 and the second conductive layer 44 are ofmetal oxide. The first conductive layer 42 and the second conductivelayer 44 are of, for example, calcium titanate, strontium titanate,barium titanate, or a composite thereof. The first conductive layer 42and the second conductive layer 44 are of, for example,(Ca,Sr,Ba)(Ti,Zr,Hf)O₃ including perovskite structure. The firstconductive layer 42 and the second conductive layer 44 are ofpolycrystal or amorphous.

The first conductive layer 42 and the second conductive layer 44 are ofthe PTCR.

It is desirable that the first conductive layer 42 and the secondconductive layer 44 contain lead (Pb). In calcium titanate, strontiumtitanate, barium titanate, and the composite thereof, by containing lead(Pb), it becomes possible to shift a region including the positivetemperature coefficient to the high temperature side.

As described above, according to the present embodiment, same as thefifth embodiment, the MOSFET is achieved of a low contact resistancebetween a drain electrode 34 and a drain region 46. In addition, same asthe fifth embodiment, the MOSFET is achieved of a low contact resistancebetween a source electrode 32 and a source region 52. In addition, sameas the fifth embodiment, the MOSFET is achieved of the low contactresistance with a relatively low temperature process.

Further, same as the fifth embodiment, to the n⁺-type source region 52and a p⁺-type well contact region 54, contact can be achieved of a lowcontact resistance by the source electrode 32 simultaneously. Further,same as the fifth embodiment, by the trench gate structure, the MOSFETis achieved of a large ON-state current.

Further, due to the fact that the first conductive layer 42 and thesecond conductive layer 44 are of the PTCR, breakdown due to excesscurrent of the MOSFET is suppressed. In particular, since the MOSFET ofthe present embodiment is of the trench gate structure, the ON-statecurrent is large. Therefore, prevention effect of the breakdown due tothe excess current of the MOSFET is particularly useful.

Seventh Embodiment

A semiconductor device of the present embodiment is different from thesemiconductor device of the third embodiment, in that the device is aMOSFET of a super junction structure. Description is omitted of contentsoverlapping with those of the third embodiment.

FIG. 7 is a schematic cross-sectional diagram illustrating aconfiguration of the MOSFET being the semiconductor device of thepresent embodiment. A MOSFET 400 is the MOSFET of the super junctionstructure in which a p-type pillar region is provided in the driftregion.

The MOSFET 400 includes an SiC layer 10, a source electrode (secondmetal layer) 32, a drain electrode (first metal layer) 34, a gateinsulating film 36, a gate electrode 38, an interlayer insulating film40, a first conductive layer 42, a second conductive layer 44. The SiClayer 10 includes a drain region (n-type first SiC region) 46, a driftregion 48, a well region 50, a source region (n-type second SiC region)52, a well contact region (p-type SiC region) 54, a pillar region 62.

The pillar region 62 is provided in the drift region 48. The pillarregion 62 is of p-type SiC.

The pillar region 62 contains, for example, aluminum (Al) as a p-typeimpurity. A concentration of the p-type impurity of the pillar region 62is, for example, equal to or greater than 5×10¹⁵ cm⁻³ and equal to orless than 1×10¹⁸ cm⁻³.

In the SiC layer 10, the n⁻-type drift region 48 and the p-type pillarregion 62 are arranged alternately in the lateral direction to form thesuper junction structure. By forming the super junction structure, anelectric field is relaxed in an OFF state of the MOSFET 400, anddielectric breakdown voltage is improved of the MOSFET 400.

The first conductive layer 42 and the second conductive layer 44 containtitanium (Ti), oxygen (O), zirconium (Zr) or hafnium (Hf), and at leastone element selected from the group consisting of vanadium (V), niobium(Nb), and tantalum (Ta).

According to the present embodiment, same as the third embodiment, theMOSFET 400 is achieved of a low contact resistance between the drainelectrode 34 and the drain region 46. In addition, same as the thirdembodiment, the MOSFET 400 is achieved of a low contact resistancebetween the source electrode 32 and the source region 52. In addition,same as the third embodiment, the MOSFET 400 is achieved of the lowcontact resistance with a relatively low temperature process.

Further, same as the third embodiment, to the n⁺-type source region 52and the p⁺-type well contact region 54, contact can be achieved of a lowcontact resistance by the source electrode 32 simultaneously.

Further, by the super junction structure, the MOSFET 400 is achieved ofimproving the dielectric breakdown voltage.

Eighth Embodiment

A semiconductor device of the present embodiment is the same as thesemiconductor device of the seventh embodiment, except that first andsecond conductive layers contain at least one metal element selectedfrom the group consisting of calcium (Ca), strontium (Sr), and barium(Ba), and that elements are different from those that can be containedin the first and second conductive layers. Therefore, description isomitted of contents overlapping with those of the seventh embodiment. Inaddition, for the configuration, function, and the like of theconductive layer, description is omitted of contents overlapping withthose of the first or second embodiment.

The semiconductor device of the present embodiment is a MOSFET. TheMOSFET of the present embodiment is described with reference to FIG. 7.

A first conductive layer 42 and a second conductive layer 44 contain atleast one metal element selected from the group consisting of calcium(Ca), strontium (Sr), and barium (Ba). In addition, the first conductivelayer 42 and the second conductive layer 44 contain titanium (Ti) andoxygen (O). In addition, the first conductive layer 42 and secondconductive layer 44 contain zirconium (Zr) or hafnium (Hf). In addition,the first conductive layer 42 and the second conductive layer 44 containat least one element selected from the group consisting of vanadium (V),niobium (Nb), tantalum (Ta), scandium (Sc), yttrium (Y), and lanthanoid.

The first conductive layer 42 and the second conductive layer 44 are ofmetal oxide. The first conductive layer 42 and the second conductivelayer 44 are of, for example, calcium titanate, strontium titanate,barium titanate, or a composite thereof. The first conductive layer 42and the second conductive layer 44 are of, for example,(Ca,Sr,Ba)(Ti,Zr,Hf)O₃ including perovskite structure. The firstconductive layer 42 and the second conductive layer 44 are ofpolycrystal or amorphous.

The first conductive layer 42 and the second conductive layer 44 are ofthe PTCR.

It is desirable that the first conductive layer 42 and the secondconductive layer 44 contain lead (Pb). In calcium titanate, strontiumtitanate, barium titanate, and the composite thereof, by containing lead(Pb), it becomes possible to shift a region including the positivetemperature coefficient to the high temperature side.

As described above, according to the present embodiment, the MOSFET isachieved of a low contact resistance between a drain electrode 34 and adrain region 46. In addition, the MOSFET is achieved of a low contactresistance between a source electrode 32 and a source region 52. Inaddition, the MOSFET is achieved of the low contact resistance with arelatively low temperature process.

Further, to the n⁺-type source region 52 and a p⁺-type well contactregion 54, contact can be achieved of a low contact resistance by thesource electrode 32 simultaneously. Further, due to the fact that thefirst conductive layer 42 and the second conductive layer 44 are of thePTCR, breakdown due to excess current of the MOSFET is suppressed.Further, by the super junction structure, the MOSFET is achieved ofimproving dielectric breakdown voltage.

Ninth Embodiment

A semiconductor device of the present embodiment is different from thesemiconductor device of the fifth embodiment, in that the device is aMOSFET of a super junction structure. Description is omitted of contentsoverlapping with the fifth embodiment.

FIG. 8 is a schematic cross-sectional diagram illustrating aconfiguration of the MOSFET being the semiconductor device of thepresent embodiment. A MOSFET 500 is a MOSFET of a trench gate structurein which a gate electrode is provided in the trench. In addition, theMOSFET 500 is a MOSFET of the super junction structure in which a p-typepillar region is provided in the drift region.

The MOSFET 500 includes an SiC layer 10, a source electrode (secondmetal layer) 32, a drain electrode (first metal layer) 34, a gateinsulating film 36, a gate electrode 38, an interlayer insulating film40, a first conductive layer 42, a second conductive layer 44. The SiClayer 10 includes a drain region (n-type first SiC region) 46, a driftregion 48, a well region 50, a source region (n-type second SiC region)52, a well contact region (p-type SiC region) 54, a pillar region 62.

The gate insulating film 36 and the gate electrode 38 are formed in atrench 60 provided in the SiC layer 10.

The pillar region 62 is provided in the drift region 48. The pillarregion 62 is of p-type SiC.

The pillar region 62 contains, for example, aluminum (Al) as a p-typeimpurity. A concentration of the p-type impurity of the pillar region 62is, for example, equal to or greater than 5×10¹⁵ cm⁻³ and equal to orless than 1×10¹⁸ cm⁻³.

In the SiC layer 10, the n⁻-type drift region 48 and the p-type pillarregion 62 are arranged alternately in the lateral direction to form thesuper junction structure. By forming the super junction structure, anelectric field is relaxed in an OFF state of the MOSFET 500, anddielectric breakdown voltage is improved of the MOSFET 500.

The first conductive layer 42 and the second conductive layer 44 containtitanium (Ti), oxygen (O), zirconium (Zr) or hafnium (Hf), and at leastone element selected from the group consisting of vanadium (V), niobium(Nb), and tantalum (Ta).

According to the present embodiment, same as the fifth embodiment, theMOSFET 500 is achieved of a low contact resistance between the drainelectrode 34 and the drain region 46. In addition, same as the fifthembodiment, the MOSFET 500 is achieved of a low contact resistancebetween the source electrode 32 and the source region 52. In addition,same as the fifth embodiment, the MOSFET 500 is achieved of the lowcontact resistance with a relatively low temperature process.

Further, same as the fifth embodiment, to the n⁺-type source region 52and the p⁺-type well contact region 54, contact can be achieved of a lowcontact resistance by the source electrode 32 simultaneously. Further,by the trench gate structure, the MOSFET 500 is achieved of a largeON-state current.

Further, by the super junction structure, the MOSFET 500 is achieved ofimproving the dielectric breakdown voltage.

Tenth Embodiment

A semiconductor device of the present embodiment is the same as thesemiconductor device of the ninth embodiment, except that first andsecond conductive layers contain at least one metal element selectedfrom the group consisting of calcium (Ca), strontium (Sr), and barium(Ba), and that elements are different from those that can be containedin the first and second conductive layers. Therefore, description isomitted of contents overlapping with those of the ninth embodiment. Inaddition, for the configuration, function, and the like of theconductive layer, description is omitted of contents overlapping withthose of the first or second embodiment.

The semiconductor device of the present embodiment is a MOSFET. TheMOSFET of the present embodiment is described with reference to FIG. 8.

A first conductive layer 42 and a second conductive layer 44 contain atleast one metal element selected from the group consisting of calcium(Ca), strontium (Sr), and barium (Ba). In addition, the first conductivelayer 42 and the second conductive layer 44 contain titanium (Ti) andoxygen (O). In addition, the first conductive layer 42 and the secondconductive layer 44 contain zirconium (Zr) or hafnium (Hf). In addition,the first conductive layer 42 and the second conductive layer 44 containat least one element selected from the group consisting of vanadium (V),niobium (Nb), tantalum (Ta), scandium (Sc), yttrium (Y), and lanthanoid.

The first conductive layer 42 and the second conductive layer 44 are ofmetal oxide. The first conductive layer 42 and the second conductivelayer 44 are of, for example, calcium titanate, strontium titanate,barium titanate, or a composite thereof. The first conductive layer 42and the second conductive layer 44 are of, for example,(Ca,Sr,Ba)(Ti,Zr,Hf)O₃ including perovskite structure. The firstconductive layer 42 and the second conductive layer 44 are ofpolycrystal or amorphous.

The first conductive layer 42 and the second conductive layer 44 are ofthe PTCR.

It is desirable that the first conductive layer 42 and the secondconductive layer 44 contain lead (Pb). In calcium titanate, strontiumtitanate, barium titanate, and the composite thereof, by containing lead(Pb), it becomes possible to shift a region including the positivetemperature coefficient to the high temperature side.

As described above, according to the present embodiment, same as theninth embodiment, the MOSFET is achieved of a low contact resistancebetween a drain electrode 34 and a drain region 46. In addition, same asthe ninth embodiment, the MOSFET is achieved of a low contact resistancebetween a source electrode 32 and a source region 52. In addition, sameas the ninth embodiment, the MOSFET is achieved of the low contactresistance with a relatively low temperature process.

Further, same as the ninth embodiment, to the n⁺-type source region 52and a p⁺-type well contact region 54, contact can be achieved of a lowcontact resistance by the source electrode 32 simultaneously. Further,same as the ninth embodiment, by the trench gate structure, the MOSFETis achieved of a large ON-state current. Further, same as the ninthembodiment, by the super junction structure, the MOSFET is achieved ofimproving dielectric breakdown voltage.

Further, due to the fact that the first conductive layer 42 and thesecond conductive layer 44 are of the PTCR, breakdown due to excesscurrent of the MOSFET is suppressed. In particular, since the MOSFET ofthe present embodiment is of the trench gate structure, the ON-statecurrent is large. Therefore, prevention effect of the breakdown due tothe excess current of the MOSFET is particularly useful.

Eleventh Embodiment

A semiconductor device of the present embodiment is different from thesemiconductor device of the third embodiment, in that the device is anIGBT (Insulated Gate Bipolar Transistor). Description is omitted ofcontents overlapping with those of the third embodiment.

FIG. 9 is a schematic cross-sectional diagram illustrating aconfiguration of an IGBT being a semiconductor device of the presentembodiment.

An IGBT 600 includes an SiC layer 110, an emitter electrode (metallayer) 132, a collector electrode 134, a gate insulating film 136, agate electrode 138, an interlayer insulating film 140, a conductivelayer 144. The SiC layer 110 includes a collector region 146, a driftregion 148, a base region 150, an emitter region (n-type SiC region)152, a base contact region (p-type SiC region) 154.

The SiC layer 110 is SiC whose crystal structure is 4H-SiC. The 4H-SiCis a hexagonal crystal system.

The SiC layer 110 has a first plane and a second plane. In FIG. 9, thefirst plane is an upper plane of the figure, and the second plane is alower plane of the figure. Hereinafter, the first plane is referred toas a front plane, and the second plane is referred to as a back plane.

Hereinafter, a case is described as an example in which the first planeis a plane inclined to a (0001) face by equal to or greater than 0degrees and equal to or less than 8 degrees, and the second plane is aplane inclined to a (000-1) face by equal to or greater than 0 degreesand equal to or less than 8 degrees. The (0001) face is referred to as asilicon face. The (000-1) face is referred to as a carbon face.

The collector region 146 is of p-type SiC. The collector region 146contains, for example, aluminum (Al) as a p-type impurity. Aconcentration of the p-type impurity of the collector region 146 isequal to or greater than 1×10¹⁸ cm⁻³ and equal to or less than 1×10²¹cm⁻³.

From a viewpoint of reducing contact resistance between the collectorelectrode 134 and the collector region 146, a concentration of thep-type impurity in the second plane of the collector region 146 isdesirably equal to or greater than 1×10¹⁹ cm⁻³, and is more desirablyequal to or greater than 1×10²⁰ cm⁻³.

The drift region 148 is provided on the collector region 146. The driftregion 148 is of, for example, n⁻-type SiC formed by epitaxial growth onthe collector region 146. Thickness of the drift region 148 is, forexample, equal to or greater than 5 μm and equal to or less than 150 μm.

The drift region 148 contains, for example, nitrogen (N) as an n-typeimpurity. A concentration of the n-type impurity of the drift region 148is equal to or greater than 5×10¹⁵ cm⁻³ and equal to or less than 2×10¹⁶cm⁻³.

The base region 150 is provided on the drift region 148. The base region150 is of p-type SiC. The base region 150 functions as a channel regionof the IGBT 600.

The base region 150 contains, for example, aluminum (Al) as a p-typeimpurity. A concentration of the p-type impurity of the base region 150is equal to or greater than 5×10⁵ cm⁻³ and equal to or less than 1×10¹⁷cm⁻³. Depth of the base region 150 is, for example, equal to or greaterthan 0.4 μm and equal to or less than 0.8 μm.

The emitter region 152 is provided in the base region 150. The emitterregion 152 is of n⁺-type SiC. The emitter region 152 contains, forexample, nitrogen (N) as an n-type impurity. A concentration of then-type impurity of the emitter region 152 is equal to or greater than1×10¹⁸ cm⁻³ and equal to or less than 1×10²¹ cm⁻³.

From a viewpoint of reducing contact resistance between the emitterelectrode (metal layer) 132 and the emitter region 152, a concentrationof the n-type impurity in the first plane of the emitter region 152 isdesirably equal to or greater than 1×10¹⁹ cm⁻³, and is more desirablyequal to or greater than 1×10²⁰ cm⁻³.

Depth of the emitter region 152 is shallower than depth of the baseregion 150, and is, for example, equal to or greater than 0.2 μm andequal to or less than 0.4 μm.

The base contact region 154 is provided in the base region 150. The basecontact region 154 is provided laterally to the emitter region 152.

The base contact region 154 is of p⁺-type SiC. The base contact region154 contains, for example, aluminum (Al) as a p-type impurity. Aconcentration of the p-type impurity of the base contact region 154 is,for example, equal to or greater than 1×10¹⁸ cm⁻³ and equal to or lessthan 1×10²¹ cm⁻³.

Depth of the base contact region 154 is shallower than depth of the baseregion 150, and is, for example, equal to or greater than 0.2 μm andequal to or less than 0.4 μm.

The gate insulating film 136 is formed on the front planes of the driftregion 148 and the base region 150. For the gate insulating film 136,for example, a silicon oxide film and a high-k insulating film can beapplied.

The gate electrode 138 is provided on the gate insulating film 136. Forthe gate electrode 138, for example, polycrystalline silicon doped withan impurity can be applied.

The interlayer insulating film 140 is provided on the gate electrode138. The interlayer insulating film 140 is of, for example, a siliconoxide film.

The base region 150 sandwiched between the emitter region 152 and thedrift region 148 below the gate electrode 138, functions as the channelregion of the IGBT 600.

The emitter electrode 132 is provided on the front plane of the SiClayer 110. The emitter electrode 132 is electrically connected with theemitter region 152 and the base contact region 154. The emitterelectrode 132 is in contact with the base contact region 154 and theconductive layer 144. The emitter electrode 132 also includes a functionof applying electrical potential to the base region 150.

The emitter electrode (metal layer) 132 is of metal. The metal formingthe emitter electrode 132 is of, for example, a laminated structure oftitanium (Ti) and aluminum (Al). The metal forming the emitter electrode132 may react with the SiC layer 110 to form metal silicide or metalcarbide.

The collector electrode 134 is provided on the back plane of the SiClayer 110. The collector electrode 134 is electrically connected withthe collector region 146.

The collector electrode 134 is of metal. The metal forming the collectorelectrode 134 is, for example, titanium nitride (TiN).

The conductive layer 144 is provided between the emitter region (n-typeSiC region) 152 and the emitter electrode (metal layer) 132. Theconductive layer 144 is in contact with the emitter region 152. Theconductive layer 144 is in contact with emitter electrode 132.

The conductive layer 144 contains titanium (Ti), oxygen (O), zirconium(Zr) or hafnium (Hf), and at least one element selected from the groupconsisting of vanadium (V), niobium (Nb), and tantalum (Ta).

As described above, according to the present embodiment, the IGBT 600 isachieved of a low contact resistance between the emitter electrode 132and the emitter region 152. In addition, the IGBT 600 is achieved of thelow contact resistance with a relatively low temperature process.

Further, to the n⁺-type emitter region 152 and the p⁺-type base contactregion 154, contact can be achieved of a low contact resistance by theemitter electrode 132 simultaneously. Since contact between theconductive layer 144 and the emitter electrode 132 becomes contactbetween metal and metal, it is possible to select a metal materialforming the emitter electrode 132 without considering the contactresistance. Therefore, as the metal material of the emitter electrode132, a metal material can be selected of reducing the contact resistanceto the base contact region 154.

Twelfth Embodiment

A semiconductor device of the present embodiment is the same as thesemiconductor device of the eleventh embodiment, except that theconductive layer contains at least one metal element selected from thegroup consisting of calcium (Ca), strontium (Sr), and barium (Ba), andthat elements are different from those that can be contained in theconductive layer. Therefore, description is omitted of contentsoverlapping with those of the eleventh embodiment. In addition, for theconfiguration, function, and the like of the conductive layer,description is omitted of contents overlapping with those of the firstor second embodiment.

The semiconductor device of the present embodiment is an IGBT. The IGBTof the present embodiment is described with reference to FIG. 9.

A conductive layer 144 contains at least one metal element selected fromthe group consisting of calcium (Ca), strontium (Sr), and barium (Ba).In addition, the conductive layer 144 contains titanium (Ti) and oxygen(O). In addition, the conductive layer 144 contains zirconium (Zr) orhafnium (Hf). In addition, the conductive layer 144 contains at leastone element selected from the group consisting of vanadium (V), niobium(Nb), tantalum (Ta), scandium (Sc), yttrium (Y), and lanthanoid.

The conductive layer 144 is of metal oxide. The conductive layer 144 isof, for example, calcium titanate, strontium titanate, barium titanate,or a composite thereof.

The conductive layer 144 is of, for example, (Ca,Sr,Ba)(Ti,Zr,Hf)O₃including perovskite structure. The conductive layer 144 is polycrystalor amorphous.

The conductive layer 144 is of the PTCR.

It is desirable that the conductive layer 144 contains lead (Pb). Incalcium titanate, strontium titanate, barium titanate, and the compositethereof, by containing lead (Pb), it becomes possible to shift a regionincluding the positive temperature coefficient to the high temperatureside.

As described above, according to the present embodiment, same as theeleventh embodiment, the IGBT is achieved of a low contact resistancebetween an emitter electrode 132 and an emitter region 152. In addition,same as the eleventh embodiment, the IGBT is achieved of the low contactresistance with a relatively low temperature process.

Further, same as the eleventh embodiment, to the n⁺-type emitter region152 and a p⁺-type base contact region 154, contact can be achieved of alow contact resistance by the emitter electrode 132 simultaneously.

Further, due to the fact that the conductive layer 144 is of the PTCR,breakdown due to excess current of the IGBT is suppressed.

In the first through twelfth embodiments, although nitrogen (N) has beenexemplified as an n-type impurity, it is possible to apply phosphorus(P), arsenic (As), antimony (Sb), and the like, instead of nitrogen (N).In addition, although aluminum (Al) has been exemplified as a p-typeimpurity, it is possible to apply boron (B), gallium (Ga), indium (In),and the like, instead of aluminum (Al).

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, semiconductor device described hereinmay be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the devices andmethods described herein may be made without departing from the spiritof the inventions. The accompanying claims and their equivalents areintended to cover such forms or modifications as would fall within thescope and spirit of the inventions.

What is claimed is:
 1. A semiconductor device comprising: an n-type SiCregion; a metal layer; and a conductive layer provided between then-type SiC region and the metal layer, the conductive layer includingtitanium (Ti), oxygen (O), at least one first element from zirconium(Zr) and hafnium (Hf), and at least one second element from vanadium(V), niobium (Nb), and tantalum (Ta).
 2. The device according to claim1, wherein an atomic ratio of titanium to sum of titanium, zirconium,and hafnium in the conductive layer (Ti/(Ti+Zr+Hf)) is equal to orgreater than 0.5 and equal to or less than 0.8.
 3. The device accordingto claim 1, wherein a concentration of the at least one second elementin the conductive layer is equal to or greater than 1×10¹⁹ cm⁻³.
 4. Thedevice according to claim 1, wherein the conductive layer contains metaloxide.
 5. The device according to claim 1, wherein a concentration of ann-type impurity of the n-type SiC region is equal to or greater than1×10¹⁹ cm⁻³.
 6. The device according to claim 1, further comprising ap-type SiC region, wherein the metal layer is in contact with the p-typeSiC region and the conductive layer.
 7. A semiconductor devicecomprising: an n-type SiC region; a metal layer; and a conductive layerprovided between the n-type SiC region and the metal layer, theconductive layer including titanium (Ti), oxygen (O), at least one firstelement from zirconium (Zr) and hafnium (Hf), at least one metal elementfrom calcium (Ca), strontium (Sr), and barium (Ba), and at least onesecond element from vanadium (V), niobium (Nb), tantalum (Ta), scandium(Sc), yttrium (Y), and lanthanoid.
 8. The device according to claim 7,wherein an atomic ratio of titanium to sum of titanium, zirconium, andhafnium in the conductive layer (Ti/(Ti+Zr+Hf)) is equal to or greaterthan 0.5 and equal to or less than 0.8.
 9. The device according to claim7, wherein a concentration of the at least one second element in theconductive layer is equal to or greater than 1×10¹⁹ cm⁻³.
 10. The deviceaccording to claim 7, wherein the conductive layer contains metal oxide.11. The device according to claim 7, wherein the conductive layercontains calcium titanate, strontium titanate, or barium titanate. 12.The device according to claim 7, wherein a concentration of an n-typeimpurity of the n-type SiC region is equal to or greater than 1×10¹⁹cm⁻³.
 13. The device according to claim 7, further comprising a p-typeSiC region, wherein the metal layer is in contact with the p-type SiCregion and the conductive layer.
 14. The device according to claim 7,wherein the conductive layer contains lead (Pb).
 15. The deviceaccording to claim 7, wherein temperature dependency of electricresistance of the conductive layer turns from negative dependency topositive dependency at a temperature equal to or greater than 150° C.and equal to or less than 200° C.